Just heard from Jan Steunebrink so I thought I'd bring you all up to date.
"Oke, I disassembled the BIOS and found the Cyrix ID lookup table.
It doesn't go any further than 54h / 5Ch (3.5x), and the Cyrix detection
algorithm is such that when it sees 55h / 5Dh it doesn't even recognise the
CPU as a Cyrix and it messes up the initialization completely!
So Peter Missel was right on this one.

I did a quick patch to test if the 4.0x mode wil work. The Cyrix ID table
uses 4 bytes for each entry. The first 2 bytes contain the DIR0 ID bytes,
the 3rd byte indicates the CPU type for the BIOS and the 4th byte the CPU
features.
At the beginning of the Cyrix ID table there was an 21h / 23h ID entry for
an early model 6x86. I've replaced this entry with the 55h / 5Dh ID bytes
for the MII in 4.0x mode and also adjusted the CPU features byte to match.
In addition I've changed the FSB byte in the CPU speed table for the 300MHz
entry from 60 to 66/75MHz. This will ensure a correct Auto configuration of
the chipset registers when you are able to run the CPU at 4.0x75MHz.
I've checked several other Cyrix init subroutines and I believe it should
work with the above changes.

Attached is a (zipped) copy of the patched BIOS. The filename is
2A59GD4J.BIN and you can flash it with the program you normally use the
flash a BIOS on this board.
Please let me know if this works, and what the BIOS indicates for CPU type
and speed on the boot and summary screens now, when you set it to 4.0x66.
Greetings,
Jan."
So I'm going to try this over the weekend...wish me luck!!
