tyan non smp boot with duall 1466(256) tualatin celerons

Recommended by Wim's BIOS...

the cpus work fine induvidually,however,ondual,the hdds powers on the vga lights goes geen infact it all seems to work but no display,obviously intel performed some magic to deliberately conn us into their overpriced (512)kb s cpus,my question is how do they implement such a pathedic practice (killing smp on non 512k tualatin cpus,is there a workaround to
enable boot on 256k tualatin cpus?,is it the bios disabling or the cpu disabling?for the ask of 1.4gs cpus,one can get duall p4 xeon+mboard with change to spare.the celeron @133fsb despite half but proven adequate 256k l2 cache trounced the 1.4s in every test in bench testing+ran cooler too.but this intel hack of a perfectly good design
killing smp ,reminds me to tell everyone that the 1.4s(512) smp cpu is not the most powerfull pentium 3 solution as far as running single cpu on servers(if one enables 133fsb from a 100fsb but indeed capable 133fsb cpu.

Beatoem, this is one of Intel's tricks for those like you not to use non-server CPU's
Anyway, the problem is one pin: AM2, isolate it on both CPUs and try again.

thanks for the input raceboy,unfortunately its still no go,regardless @1.466+1600mgz @133fsb on both workstations they noticably outperform the previous dual 1.266 +1.133 pentium s to the point i was happy to sell smp cpus +go faster + pocket some decent change too (despite assumptions) single faster speed cpu is noticably faster in most (if not all apps ive been running to date)all tualatins do have data prefetch logic (contary to bogus claims,even the celerons,and decent 256l2 cache just like all pentium3s (except the s cpus)heck even p3 xeons @133fsb came with 256l2 max,
bottom line memory bandwidth is faster ,os loading times are faster
2d+ 3d graphics are faster ,let alone on demand apps that load seemingly faster too.

If prefetching was available in Tualatin Celerons, then quite apparently not all of them:
http://www.realworldtech.com/page.cfm?A ... 231808&p=6
Unfortunately it is not stated which stepping was used.

There have indeed been PIII Xeons with 256K L2, but those were the "budget" models and most probably contained an ordinary Coppermine core (only went up to 2 procs, too, IIRC). That large L2 caches are beneficial in multi-processor operation with a shared processor bus has been shown by Intel years ago (and makes sense, too). In fact, the Xeons (or were it PPros?) with the biggest caches were specifically intended for 4-CPU configs with their very busy FSB. (4-CPU configs with Xeons also required 100 MHz max FSB clock, as if the bottleneck weren't tight enough at 133.)

This tip with AM2 is interesting. It would seem, however, that it's "reserved" for CuMines but grounded (Vss) for Tualatins, with no differences between MP and non-MP versions of the latter. Can also be left unconnected according to both datasheets. I'd check for connection to a known Vss pin, and if that should be present, then obviously it's not this pin (since 'unconnected' has already been tried with no luck). I'd guess BR1# is just not routed to X2 with the Celerons, or if it is, it's pulled up internally (as with the SEPP Celerons). I've never heard of any working SMP config with Tualatin Celerons either, except for those funky 900 MHz samples with the s-spec of 1300 MHz ones that someone got at a fair (possibly a production error struck here, leaving several internal connections open).

BTW, this is one of the least busy threads I've seen, ever. Come back a few months later and you won't have missed more than a post.

fortunately p111s specs cpus are feasably affordable nowadays,i use these today thankyou intel for the brand new 1.4s spec $7 cpus.
now i dont need to even bother with any over expensive dual cores,with dumber os system integration support,instead just load the xpsp3 cd all drivers loaded,ready on the net under 24 minutes from a clean install
now thats my idea of a true slick pc.

patience is virtue.