Tyan S1832DL (Tiger 100)

[cp]

Recommended by Wim's BIOS...

[cp]

sorry, what's cct?
just out of curiosity: are you using identical slot1 adapters or did you test them both in the CPU1 slot?

[KachiWachi]

Maybe he means ckt (circuit).

Hi,

Yes - cct (circuit) in English

Also - both the slockets are identical,
Both CPUs are identical,
Both CPUs and slockets have been tested in CPU1
as a single CPU system with terminator card in CPU2,
Both slockets now have the X2 to B75 mod in place

Still have the same problem

[cp]

okay, back to work ;)

ftp://download.intel.com/design/Xeon/da ... 966502.pdf
Page 79 explains how the BRx# pins work and how they are wired. you should be able to check this on your mainboard: BR0# is on A76 while BR1# is on B75 (as we already know. and i doubt there's something wrong there :)).
so the missing link will be to wire the adapters up so that the fcpga pins will be routed to the appropriate pins on the slot1. apparently that's already done. while reading through the Xeon i realized that BR1# must be terminated with a resistor to V_tt. so while your adapter may have AN15 to V_tt via 56Ohm (that's what you were measuring..) X2 and N33 are apparently NOT. you have to find yourself a V_tt pin on the coppermine (!) core and connect a resistor of 56Ohm to X2 in addition to the connection you already made from X2 to B75. i'd recommend AG1.

yes

With the N33 mod for Tualtin I believe 56R is on the die or,
rather, the chip package but not... on the coppermine

Again, thx for the help

Hi,

Modded both slockets with precision 56R2 across AG1 To X2
Connected B75 To X2.

Tested both as single CPU setup - both POST and boot to NT4 Server.

However, when in dual CPU mode will not boot.
The mobo status LED is amber/yellow not green as normal.

Suspect maybe VID issue or CPU uCode issue - dunno (yet).
Investigation of the mobo reveals DC-DC convertors, 1 for
each CPU. These are Fairchild RC5051M type regulator.

http://www.alldatasheet.com/datasheet-p ... C5051.html

Consider first, p10 of the above and Fairchild Application Note 53 p4.
Both refer to PWRGD and OE (power good and output enable).

Q - Does the CPU uCode update I applied for SL5QV (068A) apply to
both CPUs being that I have modded (correctly I assume) the slockets
for dual CPU use.

If not, CPU2 might not supply correct VID - result
no power good and no O/P enable but... I am guessing.
Anyway, I suspect if it were simply this, at POST (if it were to post)
I would get a uCode error.

I have a POST diag card and find +12, -12V, +5 (-5V/+3.3V) are all
good but systems sits at RESET i.e. code 0000 when dual CPU.

Guess I'll have to get a logic probe and see what the regualtors
are doing!

Help and/or comments please

[cp]

the cpu µcode update does nothing to the VID pins. they are set statically during the process of packaging the die and the cpu tray.
one thing makes me wonder: the PC5051 supports 5bit VID and thus voltages downto 1.3v. but as you wrote in one of your last posts the voltage readout shows 1.8v even though it should be 1.7v as defined by the cpu. can you please take a multimeter and measure the volatage at one of the FETs? i don't really trust the accuracy of those onboard voltage readouts. you can test the VID pins at the regulator with a DMM, too. nothing fancy there, just high and low signals. nothing inbetween.
i still suspect the 2nd cpu not to be initialized on the multi cpu bus correctly.

Be aware with the 56R2 mod in place with a CPU in the slocket
the reading is only 28R!

Checked a similar situation with the A15 pin which we know this
slocket supports. Guess what? When the CPU is out of the slocket
reads 114R5 or so. With the CPU in the slocket does read 56R approx!

This is my oversight - oops...

I will get 113R5 for the mod to ensure 56R2 across X2 and B75 tied
to AG1 with CPU in situ. This may be the problem as B75 (like
discussed) requires this termination to latch.

Will test the O/P voltage as a matter of course and establish what
the voltage reading(s) are

ust a small update

To develop 56R across these pins - I require a 100K
value across the connection as the root cause of the
problem above is having another 56R in parallel with the
connection I seek to develop!

Duh... Do I feel stupid or what?

On the front of the slocket - there a number of quad dip
resistor packs - these are surface mount. Taking a
reading across several returns 55.5/56R as well as
28.1R.

Taking a measure across AG1 to B75 I get 56R approx.
So.. We have our 56R as required and BR1 is pulled up to Vtt.
This is required for Coppermine operation.
I require to link X2 to B75 as originally we did.

I now read 56.6R from AG1 to X2

Hi,

Have finally got round to measuring some voltages to check
the regulation is ok.

So.. CPU2 populated CPU1 has blank

The Fairchild RC5051M Regulator for CPU1 reads for the VID (tst in cct)
ID = VID4 VID3 VID2 VID1 VID0
Pin = 8 17 18 19 20
Val = 0 0 1 1 0 = 1.75V

Pin 5 = Vout = 1.79V
Pin 13 = 11V
Pin 7 = 5V

The Fairchild RC5051M Regulator for CPU2 reads for the VID (tst in cct)
ID = VID4 VID3 VID2 VID1 VID0
Pin = 8 17 18 19 20
Val = 1 1 1 1 1 = No CPU

When I populate CPU1 and place a blank in CPU2
the readings are the same only the CPUID differs - as would be expected

So it appears that the readings from the NatSemi monitor were ok

Ok... Have got some readings with both CPU1 and CPU2 in situ

The Fairchild RC5051M Regulator for CPU1 reads for the VID (tst in cct)
ID = VID4 VID3 VID2 VID1 VID0
Pin = 8 17 18 19 20
Val = 0 0 1 1 0 = 1.75V

Pin 5 = Vout = 1.8V
Pin 13 = 11.6V
Pin 7 = 5V
Pin 2 = 2.83V Enable
Pin 3 = 4.94V Power Good
Pin 9 = 2.33V LoDrv
Pin 12 = 4.85V HiDrv


The Fairchild RC5051M Regulator for CPU2 reads for the VID (tst in cct)
ID = VID4 VID3 VID2 VID1 VID0
Pin = 8 17 18 19 20
Val = 0 0 1 1 0 = 1.75V

Pin 5 = Vout = 1.48V
Pin 13 = 11.6V
Pin 7 = 5V
Pin 2 = 2.83V Enable
Pin 3 = 0.28V Power Good
Pin 9 = 2.61V LoDrv
Pin 12 = 3.74V HiDrv

Obviously then, the problem is with the regualtor for CPU2 or, when both
CPUs are in cct, the regulator for CPU2 cannot synth enough voltage to drive the FETs to the voltage ID specified hence powergood in low state

Some redesign required I think!

[edwin]

Happy tinkering for the rest of your X-mas break, you do have enough work by now