Gigabyte GA-6VXDC7 v1.0 Mobo

Questions that don't belong in the other forums.
Post Reply
JEWilson
Chip off the ol' block
Posts: 109
Joined: Wed Oct 11, 2006 12:51 am

I have been trying to extract the BIOS image - F7 beta
to detemine the cpu ucode updates (if any).

This is a 256k compressed image
Only MMTool 2.22.1 can open the image, all later versions issue an
error. However, when the bios file is loaded, no modules or BIOS
details are shown.

Is this due to the specifics of Gigabyte BIOSes?

Please advise

Thx
cp
BIOS Guru
Posts: 1914
Joined: Mon Oct 21, 2002 9:07 pm
Location: Germany

standard amibios. use amibcp to open and edit it. make sure to enable all the useful bios options they are hiding there in the advanced section!

there are cpu microcodes inside but why alter them anyway?
If you email me include [WIMSBIOS] in the subject.
JEWilson
Chip off the ol' block
Posts: 109
Joined: Wed Oct 11, 2006 12:51 am

I do not want to alter them

Seeking to determine if coppermine support for SL5FQ (FC-PGA2)
is present as well as possibility of Tualatin support

Of course, the latter would be subject to the VRM being able
to power Tualatins as well as further, it will probably be necessary
to use a Lin-Lin adaptor

Thanks
edwin
The Hardware Archivist
Posts: 6286
Joined: Wed Mar 20, 2002 7:11 pm
Location: Netherlands
Contact:

There's no difference between release 1.0 and 5.0 where it comes to CPUs. Tualatin is a no-no.

http://www.gigabyte.com.tw/Support/Moth ... uctID=1424

http://processorfinder.intel.com/Detail ... Spec=SL5FQ
is a 1GHz Coppermine if I'm not mistaken, which is supported. Lucky you :D
edwin/evasive

Do not assume anything

System error, strike any user to continue...
JEWilson
Chip off the ol' block
Posts: 109
Joined: Wed Oct 11, 2006 12:51 am

From pp.7-8 of the manual for the v1.0 mobo
The multipier can be up to x16.

The manual does suggest support for clock speeds higher
than 1GHz and jumper selection can be set to suit.

From p.13 of the manual at item 22, PIII 1GHz FSB 133 (Coppermine supported)
SW1 is set for 133MHz FSB, PCI 33MHz
SW2 sets the multiplier for x7.5

The question then re - Tualatin support is one whether (not) the CPU
VRM can support down to Tualatin voltages, e.g. an SL5XL is 1.45V
Tualatin (PIII-S) 1.4GHz FSB 512k cache.

Looking at the motherboard the VRM PWM Controller, there exists
an Intersil HIP6303CB, on p.3 of the datasheet, VIDS can dial up
1.3V - 2.05V. So, theoretically the above 1.45V part may work.

Of course, given the above details, it remains a fact this mobo
only supports FC-PGA or FC-PGA2 (SL5FQ) and that FC-PGA2 Tualatins
would require a socket adapter to map the latter to the former.

Further, it may be, the I/P and O/P side capacitors in the VRM are
insufficient for Tualatins albeit comparing the thermal design power
parameters of both chips finds, the SL5FQ at 29W and the SL5XL at unknown
(to date).

Also, the thermal guidelines favour the Tualatins as they produce
less heat, e.g. SL5FQ 75 deg C and SL5XL 69 deg C. This is probably
due to the heatspreader on the package.

Lastly, if the uCode with the latest F7 beta BIOS does not contain support
for Tualatins as above i.e. with a stepping of TA1, I would seek
to add these to the BIOS

This was the basis of my original enquiry.

Thx
edwin
The Hardware Archivist
Posts: 6286
Joined: Wed Mar 20, 2002 7:11 pm
Location: Netherlands
Contact:

Yeah well, in my personal experience, CPU support, memory support etc can change over time. I tend to use the latest available info as that manual may have been written before >1GHz Coppermines were released...
edwin/evasive

Do not assume anything

System error, strike any user to continue...
cp
BIOS Guru
Posts: 1914
Joined: Mon Oct 21, 2002 9:07 pm
Location: Germany

once more: tualatin (or any other cpu) support has nothing to do with any microcode updates. microcode updates are somewhat useless in the bios as they are loaded with any (modern) OS anyway and only fix small issues that occur in VERY VERY VERY special situations.
from the coppermine to tualatin intel modified the processor interface in some way that _could_ have damaged (or prevented stable operation) older mainboards (for various reasons) or the cpu itself. so they took some pins on the processor and moved them to different positions. CHECK THIS LIST!
let's take AJ3. on the coppermine and earliers cores it was VSS (ground). on the tualatin it's RESET2#. the # at the end of the signal name means that this signal is low active. so if you insert a tualatin processor in a socket that was designed for coppermine and earlier cores RESET2 will be low all the time which means your tualatin will remain in reset state all day long.

tualatin support depends on the electric design of the socket, not on microcode updates in the bios. the same applies for any slot1 adapters, too. so you may want to mod your cpu socket to have tualatin support. or you mod the cpu itself like some sellers on a large internet auction platform do : Image
If you email me include [WIMSBIOS] in the subject.
edwin
The Hardware Archivist
Posts: 6286
Joined: Wed Mar 20, 2002 7:11 pm
Location: Netherlands
Contact:

Thank you for the further explanation of what I was basically saying.
edwin/evasive

Do not assume anything

System error, strike any user to continue...
JEWilson
Chip off the ol' block
Posts: 109
Joined: Wed Oct 11, 2006 12:51 am

Cp

Y - I am aware of the electrical differences between Tualatin and
coppermine. I have seen others change the pin assignments (in line
with your pic.) on Tualatin FC-PGA2 package to suit the earlier FC-PGA pin out.

In fact, I believe I stated I would use a socket 370 FC-PGA2 to FC-PGA
adapter which maps the correct pins such that a Tualatin will theoretically
work provided;

The on-board VRM can step down to the lower voltages supported by
Tualatins and moreover, do this reliably under heavy load;
so... chk the CPU VRM make and model to determine if can support these VIDs.
Also, chk. the power MOSFETs can capably deliver req'd power under load.

uCode updates are the last thing to be of concern in this scenario.

Simply, I sought to establish if, the latest and last F7 Beta BIOS had
the correct uCode patches to support Tualatin steppings.

I have used BCP760 as suggested to enable a number of the BIOS
settings as suggested. I have further extracted the P6 uCode with
this BIOS but have been unable to read them thus far.

Is there a utility available to decode and read the extracted uCode
from this generation of AMI BIOS?

Thx in advance for any/all advice advanced
cp
BIOS Guru
Posts: 1914
Joined: Mon Oct 21, 2002 9:07 pm
Location: Germany

information about microcode updates are available from intel. there is a whole chapter (8.11 MICROCODE UPDATE FACILITIES) in their 'Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A: System Programming Guide, Part 1' available from their site. the format of the microcode updates is described in there.
i wrote a tool that converts the microcode updates released by intel in txt format to the binary format a mainboard bios can handle (and some redmond-born OS uses). however i never released the tool to the public (and i probably never will).
If you email me include [WIMSBIOS] in the subject.
JEWilson
Chip off the ol' block
Posts: 109
Joined: Wed Oct 11, 2006 12:51 am

Cp, thanks for the input

I have in fact determined a copy of the F7Beta BIOS has been
patched for he purpose of the project I have in mind.
As I cannot read the extracted uCode binary I possess,
I assume this patched BIOS has the correct 06B1a and 06B4h CPUID.

As I recall, BIOS extracts are in assembler and I may
require to disassemble this code to get the details. Then again,
as it has been some time since I did this, I may be wrong.

I found this on eBay Austria web page as with;
http://cgi.ebay.at/Lin-Lin-Adapter-1400 ... 240%3A1318

There is a list of motherboards that support the LinLins370 adapter
as well as with slockets.

Thanks
cp
BIOS Guru
Posts: 1914
Joined: Mon Oct 21, 2002 9:07 pm
Location: Germany

As I recall, BIOS extracts are in assembler and I may
require to disassemble this code to get the details.
no, they are in the format that the intel document i quoted describes. there's a 48 byte header followed by the microcode data. the 4 byte processor signature (cpuid) is at offset 12. the microcode data size is at offset 28. if it is 0 the microcode data size is 2000 bytes. you'll find that all microcode updates for older cpus (pre-core2) have a size of 2000 bytes and thus a 0 at offset 28. anyway, after datasize + 48 bytes header the next header starts. pretty easy stuff ;)
If you email me include [WIMSBIOS] in the subject.
Post Reply