IBM Thinkpad 600E bios mod for processor update

Don't ask how to hack password. (BIOS Passwords)
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Sharedoc
Notebook Genius
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Mon Aug 18, 2003 9:04 pm

My Thinkpad 600E (type 2645-4A0) originally comes with Intel PentiumII 366 MHz processor (MMC-2/Dixon core). I plan to change it to PentiumIII 450 - processor, which is known to run ok on 600E, but will generate error 127 (Cache error) in bios post phase. Anyway with a couple of clicks the bios starts to boot operating system.

Official support for PentiumIII comes in Thinkpad 600X series.

My question is how to open the IBM bios binary file for 600E and 600X and compare them

http://www-3.ibm.com/pc/support/site.ws ... SHY-46HLKQ
http://www-3.ibm.com/pc/support/site.ws ... IGR-4FYS2U

I have tried Award tools (CBROM, MODBIN, MODBIN2, MODBIN6) which don't seem to work for IM bios.
ajzchips
El cheapo dude
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Tue Aug 19, 2003 3:16 am

I suppose you've already tried the latest BIOS update. Anyway, is the external cache totally disabled when you try diagnostic utilities in Windows? Tried using the pep15.pdb microcode update utility?

BTW, a year ago this was posted regarding your nick:

http://www.wimsbios.com/phpBB2/viewtopi ... t=sharedoc

...same "Sharedoc"?
Sharedoc
Notebook Genius
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Tue Aug 19, 2003 4:32 pm

Yes I am the same Sharedoc.

I received the PIII-processor today, so I will install it and come back later with more information.
Sharedoc
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Tue Aug 19, 2003 6:06 pm

WCPUID (version 3.0d) shows

Mobile Pentium III
Family 6 Model 8 stepping 1

System clock 99,67
Internal clock 448,51

L1-I cache 16k
L1-D cache 16k
L2 cache 0k

cache info

No L2 cache
Sharedoc
Notebook Genius
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Tue Aug 19, 2003 9:21 pm

I found a solution how to set L2 on in Windows: PowerLeap CPU Control Panel can force L2 cache on and it works.

http://www.powerleap.com/downloads/PLea ... _0_0_1.exe

edit

looks like they changed the link

http://www.powerleap.ca/Downloads/PLeap ... _0_0_1.exe
Last edited by Sharedoc on Thu Feb 10, 2005 12:36 am, edited 1 time in total.
ajzchips
El cheapo dude
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Tue Aug 19, 2003 9:39 pm

If I were you, I'd read this:

http://www.digit-life.com/articles/cpuerrata/

...and use the pep & checkup5 combo.

It's non-destructive, since it doesn't flash your BIOS. It adds direct support for certain microcodes your BIOS doesn't seem to currently provide. This would load your OS faster, since the L2 cache would be activated during POST, not requiring the use of the PowerLeap utility.
Sharedoc
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Wed Aug 20, 2003 1:03 am

checkup5 & pep.dat reported that bios did not support microcode loading. So allowed temporary load on microcode and went back to dos (booting from harddrive didn't work immediately after checkup5 finished). From dos with ctrl-alt-del I booted but the bios post gave the same 127 error.

However, the microcode patch was still in the processor, since rerunning the checkup5 showed tha the patch was there.

So it seems that the microcode patch availale does not cure the problem with IBM bios not correctly turning on L2 cache.

What I could do now? I detected that the powerleap utility has a kernel driver VpleapD.vxd, which contains somewhere the code to turn on L2. Propably by writing MTRR registers. Disassembling ...
ajzchips
El cheapo dude
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Wed Aug 20, 2003 11:20 am

Weird... the utility works correctly on AWARD, AMI and ACER BIOSes I've tested it on in the past.
Sharedoc
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Wed Aug 20, 2003 1:29 pm

It seems that the utility works in inserting the microcode patch, but it may be that this is not solving the problem inside IBM bios code in turning on L2 in a right way for PIII.

Anyway, I will try next to find a CMOS bit that disable L2 cache. This may work, since there is hex editor in IBM bios which allows to read/write CMOS data. One of the bits might control L2 turn-on/turn-off.
Sharedoc
Notebook Genius
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Wed Aug 20, 2003 11:27 pm

I checked modifying manually the following bytes/bits from CMOS which are propably dealing with cache

2CH FD -> BD -- disable internal cache
2DH 10 -> 14 -- disable internal cache
3BH 0 -> 03 -- enable internal and external cache

None of them help. So I am starting to believe, that the problem is inside the IBM bios code setting up the caches in a PII way instead of PIII way.
edwin
The Hardware Archivist
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Thu Aug 21, 2003 12:43 am

Which would make perfect sense as the voltage regulators wre designed in with the P2 not P3 in mind.
edwin/evasive

Do not assume anything

System error, strike any user to continue...
Sharedoc
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Fri Aug 22, 2003 10:43 am

Now I have additional problem. I detected that after installing the PIII processor the memory bus is now 100MHz. I have a problem that if I use 2 128M Sodimm memories, I get sometimes bluescreen memory errors. If I use only one Sodimm, then there is no problem. Using WPCREDIT I detected that BX chipset is running with CAS latency 2. WPCREDIT allows to force CAS -> 3, but system freezes immediately. I tried other tools as well: Powertweak, Tweakbios. It seems that you cannot change CAS in windows. I wonder if it can be done in dos or using a boot floppy?
Sharedoc
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Fri Aug 22, 2003 5:12 pm

Changing CAS2 -> CAS3 turns out to crash whether you do it from windows, dos or even from boot floppy.

I really have to get into the IBM Thinkpad bios somehow...
Sharedoc
Notebook Genius
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Sat Aug 23, 2003 10:19 am

I managed to open partly the Thinkpad bios using Bios1.35.1 utility from www.geocities.com/mbockelkamp. Greeting to mbockellamp, much appreciated.

So I got out binary code for Plug and play bios v1.0.

The utility shows that there is more
- PCI bios v2.10
- IBM/MS int13 ext v1.0
- System management bios v2.2
- Desktop man Int v2.2
- Vesa bios ext v2.0
- VBE Power man v1.0
- VBE ace not activated
- PCMCIA Socket serv not activated

I am studying the P&P biox for L2 cache setting to find what bits in CMOS IM is using to control L2 setting.

Anybody have binary code PCIbios v2.10? I need to study it to find the bit in CMOS that controls the CAS2/CAS3 setting.
Sharedoc
Notebook Genius
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Sat Aug 23, 2003 7:15 pm

Finnally I got rid of annoying 127 error in bios post. The trick was to edit CMOS byte 20 to value 0A (Originally 02). It seems that bit 5 controls L1 cache and bit 4 controls L2 cache.

Continuing to find the bit that controls CAS2/CAS3 setting...
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