[Done] GA-5AX: Performance updates

Only for programmers and BIOS gurus with technical questions.
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In addition to my problem with Norton Ghost on motherboards using ALi Aladdin V chipset described in another post, I have two other issues with my GA-5AX:
1. I got my hands on one of those rare boards using revision H of Aladdin V chipset. This revision has a working internal tag RAM!
However, Gigabyte didn't enable it as I confirmed by looking at chipset registers under Win98SE. Instead, they continued soldering an external tag RAM chip onto their boards and using it:
GA-5AX Offset 40
GA-5AX Offset 41
In contrast, Asus with their P5A (Rev. 1.06!) and Jetway with their 542C used revision G of ALi Aladdin V and they didn't solder additional tag RAMs anymore. Instead, they used the internal one and set chipset registers accordingly:
542C Offset 40
542C Offset 41
I already tried to activate the internal tag RAM of my GA-5AX under Win98SE but it always ended up with a system hang, rebot, or BSoD. I guess enabling is best done during P.O.S.T.

Reading Jan Steunebrink's remarks to the 542C BIOS patch led me assume that he has experiences in editing chipset register settings in the BIOS. I already wrote him an email but I don't know if his email address is still up to date. Therefore, I post my queries here, too.
Is it possible to configure GA-5AX's BIOS that it sets the following registers during chipset initialisation in such a manner as it is done by the Jetway 542C?:
- Offset 40 to Hex 53 (Bin 01010011) -> bit #6 activates internal tag RAM when set to 1
According to the datasheet ALi M1542/M1542 (http://www.hard-net.de/info_wissen/chip ... -M1542.pdf), the BIOS first decides the state of internal tag RAM (index 40h, bit 6) by the HA[23] at powering on then it can be read and written.
- Offset 41 to Hex 05 (Bin 00000101) -> bit #0 deactivates external tag RAM when set to 1
I don't know whether it is possible to use internal and external tag RAM at the same time. I would give it a try and test it. May be it is possible to create an option in SETUP where you can select between internal, external, or both tag RAMs.
- Offset 43 to Hex F7 (Bin 11110111) -> bit #7 enables Force Snoop INV when set to 1; bit #1 enables Fast NAJ when set to 1
GA-5AX Offset 43: Image
542C Offset 43: Image

And a second question: the BIOS configures SDRAM RAS Precharge time (tRP) at 4T for all FSB settings faster than 83 MHz. However, 2T also seems to work.
Do you think it is possible to set
- Offset 48 to Hex 1E (Bin 00011110)
for all FSB frequencies during chipset initialisation by the GA-5AX BIOS?
GA-5AX Offset 48@FSB100:
542C Offset 48@FSB100:
Would you be interested in doing these modifications to unleash the full power of the chipset?
I will do testings of the new BIOSes after each step.
Maybe some of the options can be made accessible in the BIOS setup?
If you know any additional improvements you are welcome to implement them. I will do testings.
Last edited by Lotosdrache on Sun Feb 23, 2020 10:18 pm, edited 1 time in total.
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So, here I am again having a big smile in my face :D

I finished the injection on Thursday. What was so difficult last year was so easy now many month later :)
Pinczakko's guides here just gave me so much information that I could not see the forest for the trees :roll:
Sadly, the minor patch for lowering RAS Precharge Time that looked to be so easy didn't work. It seems the register is locked or the value is overwritten by code executed later. I have to study the datasheet again for this :?
The much more important patch for switching from external to internal Tag RAM on my Gigabyte GA-5AX Rev 5.2 with Aladdin V chipset Revision H, however, works flawlessly :D

This was the configuration before with Gigabyte's BIOS version GA-5AX F4:
03 BIOS F4 K6-2 400 mit L3 kein DOS-Treiber - 0.jpg
As you can see:
- Secondary Cache (L2) = 512 KByte, direct mapped
- Cacheable Area L2 = 128 MByte < main memory!!

And now, with BIOS version F5 Powered by Lotosdrache :wink: :
11 BIOS F5 K6-2 400 mit L3 ohne DOS-Treiber - 0.jpg
- Secondary Cache (L2) = 512 KByte, direct mapped
- Cacheable Area L2 = 512 MByte, no noncacheable areas found :twisted:

Tests were performed with AMD K6-2/400AFQ (CXT core) having no own internal L2 cache and 512 MiB RAM in total.
Latest experiments to make the patch switchable in the BIOS-Setup failed and indicated that the values from the setup aren't loaded at all at the moment the patch is executed. So, may be I can remove those lines from the code that backup/restore BIOS-Setup settings.

Note, this is not a performance update and was never thought to be one. It's just a functional update for techies 8)

Darmawan M S a.k.a Pinczakko, Thanks a million for your great guides! I read them several times and didin't unterstand 1% of the experiences you have collected and written down there :wink: Nevertheless, they gave me all the information I needed. 8)
Thanks a lot also to Mr. Scott from overclockers.com for providing me with the PCR files! 8)
Last but not least, Thanks to Skalabala from vogons.org for bringing me back to this board at the right time just when I was relaxed enough to see the forest for the trees again! :)
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