Ok never mind my earlier query about L2 cache - thought I'd just add the info I found to the thread for prosperity.
After buying what I thought was a 600MHz P3 w/ 256Kb L2 Cache and actually getting a Cel w/ 128Kb I thought I'd add a little guide to identifying which are which from the part numbers.
Example: PMN60001201AB
PM=Processor Module
N=Intel Celeron processor Mobile Module (MMC-2)
600=600 MHz
01=128 KB Cache
201=201 Notifiable Design Revision
AB=AB Notifiable Processor Revision
So the little 01 in bold is the bit to look for; 01=128Kb L2 Cache 02=256Kb
**************************************************
Still want to explore the possibility of writing a small boot time app for windows to re-enable the L2 - I know powerleap isn't that big in memory, but it still bugs me a little. Any ideas (volunteers) as to where to start?
IBM Thinkpad 600E bios mod for processor update
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brokencase
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"Still want to explore the possibility of writing a small boot time app for windows to re-enable the L2 - I know powerleap isn't that big in memory, but it still bugs me a little. Any ideas (volunteers) as to where to start?"
The Linux kernel sources under the /arch/i386/boot directory. They show how to id and init just about any CPU. The setup.c file is what you want to look at. I am refering to 2.4 sources. 2.6 might be different.
I was looking them over last night and the kernel boot parameter to overide the cache detection is "cachesize=". I groveled throught the source but I can't see where this actually alters the cache initialization. This is why I had asked if anybody has tried this with the 600e w/PIII mod. I am not sure if it works.
My PIII is on it's way. I will post how I made out with all this running under linux..
The Linux kernel sources under the /arch/i386/boot directory. They show how to id and init just about any CPU. The setup.c file is what you want to look at. I am refering to 2.4 sources. 2.6 might be different.
I was looking them over last night and the kernel boot parameter to overide the cache detection is "cachesize=". I groveled throught the source but I can't see where this actually alters the cache initialization. This is why I had asked if anybody has tried this with the 600e w/PIII mod. I am not sure if it works.
My PIII is on it's way. I will post how I made out with all this running under linux..
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beatoem
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[quote="brokencase"]"Still want to explore the possibility of writing a small boot time app for windows to re-enable the L2 - I know powerleap isn't that big in memory, but it still bugs me a little. Any ideas (volunteers) as to where to start?"
we are working on it,think of it as the ibm 600z development forum
,i sent sharedoc some bios files to compare cpu id strings,theres also an expert on hand whom offered the best professional advice too,it doesn't get any better than this.sure one can buy a 600x,but then again a tp600e
with 108fsb and over is obviuosly faster than any tp600x anyway(HENCE 600Z),once a beta bios can be sorted ,then we can all do away with the xtra settings to enable l2 cache.whilst plleap software does a good job for windows,the bios method would help linux users too.
*sharedoc,did the files arrive ok?i purchased a 600e mainboard ,but its a 50/50 chance doa/no wty,do you know any place that shows exactly where the bios chip is located +THE MBOARD VOLTAGE REGULATOR YOU MENTIONED WHERE ABOUT IS THAT?
need to explore all possibilities to salvage mobo.
we are working on it,think of it as the ibm 600z development forum,i sent sharedoc some bios files to compare cpu id strings,theres also an expert on hand whom offered the best professional advice too,it doesn't get any better than this.sure one can buy a 600x,but then again a tp600e
with 108fsb and over is obviuosly faster than any tp600x anyway(HENCE 600Z),once a beta bios can be sorted ,then we can all do away with the xtra settings to enable l2 cache.whilst plleap software does a good job for windows,the bios method would help linux users too.
*sharedoc,did the files arrive ok?i purchased a 600e mainboard ,but its a 50/50 chance doa/no wty,do you know any place that shows exactly where the bios chip is located +THE MBOARD VOLTAGE REGULATOR YOU MENTIONED WHERE ABOUT IS THAT?
need to explore all possibilities to salvage mobo.
Brokencase,
I was not able to figure out from Intel specs how the speedstep control circuit works in detail.
Of course it would be nice to trigger the state transition to higher speed also when booting with AC power supply and every time.
I welcome any effort to figure it out.
I was not able to figure out from Intel specs how the speedstep control circuit works in detail.
Of course it would be nice to trigger the state transition to higher speed also when booting with AC power supply and every time.
I welcome any effort to figure it out.
Beatoem,
I received 4 emails with bios image files ok. I have to delay study of the files to weekend due to working overtime this week.
On the lower side of motherboard, near USB-connector, there is a Maxim MAX1632-regulator for 3.3V (Vio) and 5 volts.
http://pdfserv.maxim-ic.com/ds/en/MAX1630-MAX1635.pdf
3.3V output is pin 2 and can be found from several capacitors nearby.
Bios-Flash chip is of type Intel F28004. It is located on the top side of motherboard under the processor cooler assembly. It ptopably has a white paper sticker on it with the bios revision code and (c) IBM.
I received 4 emails with bios image files ok. I have to delay study of the files to weekend due to working overtime this week.
On the lower side of motherboard, near USB-connector, there is a Maxim MAX1632-regulator for 3.3V (Vio) and 5 volts.
http://pdfserv.maxim-ic.com/ds/en/MAX1630-MAX1635.pdf
3.3V output is pin 2 and can be found from several capacitors nearby.
Bios-Flash chip is of type Intel F28004. It is located on the top side of motherboard under the processor cooler assembly. It ptopably has a white paper sticker on it with the bios revision code and (c) IBM.
http://zurich.csail.mit.edu/hypermail/t ... /0103.html
Quote
"The TP600E bios is too old and does not enable the L2 cache.
So if you plan on using Linux, you should take the following steps
to take full advantage of the PIII.
1:Create a small DOS partition at the beginning of the HDD.
(10MB is enough)
2:Install DOS(FreeDOS, DR-DOS or whatever)
3:Boot DOS first
4:Enable L2 cache using a DOS app called 'cache-enabler 1.20'
...
5:Load the Linux kernel using loadlin."
Problem is I don't know where to get cache-enabler 1.20. I have to try if my own code "k63l2on" works as is or modified.
Quote
"The TP600E bios is too old and does not enable the L2 cache.
So if you plan on using Linux, you should take the following steps
to take full advantage of the PIII.
1:Create a small DOS partition at the beginning of the HDD.
(10MB is enough)
2:Install DOS(FreeDOS, DR-DOS or whatever)
3:Boot DOS first
4:Enable L2 cache using a DOS app called 'cache-enabler 1.20'
...
5:Load the Linux kernel using loadlin."
Problem is I don't know where to get cache-enabler 1.20. I have to try if my own code "k63l2on" works as is or modified.
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brokencase
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Sharedoc, thanks for the link, but I think I want to explore the "Linux Only" option before I attempt the "Cache Enabler" method.
Here is what the kernel docs state about the cachesize option:
cachesize=[BUGS=IA-32] Override level 2 CPU cache size detection.
Sometimes CPU hardware bugs make them report the cache
size incorrectly. The kernel will attempt work arounds
to fix known problems, but for some CPUs it is not
possible to determine what the correct size should be.
This option provides an override for these situations.
Here is what the kernel docs state about the cachesize option:
cachesize=[BUGS=IA-32] Override level 2 CPU cache size detection.
Sometimes CPU hardware bugs make them report the cache
size incorrectly. The kernel will attempt work arounds
to fix known problems, but for some CPUs it is not
possible to determine what the correct size should be.
This option provides an override for these situations.
I moved this here. This post was misplaced.brokencase wrote:Well, I do not think the cachesize parameter will work.
This seems like it was made for the Tulatin which could have 512k or 256k. In any case the cachesize parameter only alters the reported cache size. The kernel does not init cache and it expects the bios to do this.
However there is a Linux bios project on Sourceforge.net
Browsing the cvs here shows some cache init code. Looks simple enough.
http://cvs.sourceforge.net/viewcvs.py/f ... iew=markup
I think the problem is simply that the tp600e bios fails to id the cpu properly and does not bother to init the cache.
If this is the case then maybe the above code would resolve the issue. However, this code is assuming init a early bios stage. Once the cpu is up and running things are more complex. Maybe need to invalidate the cache beforehand and afterwards; just to be safe.
If I have stated the obvious forgive me...
In any case, I am happy to patch the bios bit for the near term.
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brokencase
- BIOS Newbie
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There is a solution to the cache problem under Linux here:
ftp://sunsite.unc.edu/pub/Linux/system/hardware/
cachectl-1.0.tar.gz
The cpu instructions required to enable the cache are not availible in user space. The author provides two solutions. The loadable kernel module looks the most promising.
I am going ot see if I can get these built for the 2.6 kernel.
ftp://sunsite.unc.edu/pub/Linux/system/hardware/
cachectl-1.0.tar.gz
The cpu instructions required to enable the cache are not availible in user space. The author provides two solutions. The loadable kernel module looks the most promising.
I am going ot see if I can get these built for the 2.6 kernel.