IBM Thinkpad 600E bios mod for processor update

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brokencase
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Here are the mobile PIII's specs The 500 does not have speed step.
http://www.eonet.ne.jp/~sawarabi/siryou ... _sspec.htm

Spoke to the chalet (author of the other cache enabler module) a week ago on the linux thinkpad list. I posted that I put together a cache enabler for the PIII 600e and he responded that he had done the same. Wish I had searched the web better. Oh well, it was worth the learning experience. I now know how to write modules for linux!

What was funny was that we both took the Linux BIOS route to get there.

Did'nt know that his would work with 2.6 Not that it is hard to convert a module to 2.6 as I soon found out.
Sebi
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I don´t think the cache enabling routine is the problem. Both PII and PIII belong to the same family (P6), so cache enabling is neccessary for both of them.

I looked at the disassembly from the cache enabling module and tried to find such code in the TP bios. And there is a cache enabling routine in the bios. I also compared the 600x bios with the 600e bios - the routines are the same. For those who want take a look: in the 600e bios, cache init routines start at file offset 0x44413, in 600x bios at 0x44654 (several routines, first, the MTRRs are set up, then cache is enabled).

So the error 127 is triggered before the cache get´s initialized and might only be related to cpuid or things like that. Unfortunately, I found the cache init, but not where it´s called from and also no reference for the 127 error (well, fond the string "127"... ;o)) I tried to delete the cpucard serial no - with no success.

Sharedoc: how did you find out the bios byte to change? Do you have any information where the 127 error is triggered?

Cheers,
Sebi

PS: As for the SpeedStep: what happens if you load a SpeedStep utility within windows or enable linux speedstep? Are you able to achieve higher clock rate?
Sebi
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Maybe I found another hint: the bios also contains a microcode uploader. These microcodes are model-specific, so the bios fails to update the microcode on the new cpu. Maybe that triggers the 127? Any chances to just leave alone the microcode, but do the cache?

Sebi
swsnyder
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Hello.

Inspired by the discussion here, I've decided to upgrade the processor of my ThinkPad 600E 2645-57U. I'm going to replace the P2/300 with a P3/500.

I've opened a number of notebook computers and found them to be inevitably byzantine in their design. I'd just as soon avoid the learn-by-breaking route if possible.

Is there a guide on how to get into the 600E, specifically on getting to the MCC-2 module? Any noteworthy gotchas I should know about?

Thanks.
Sebi
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swsnyder wrote:Hello.
Is there a guide on how to get into the 600E, specifically on getting to the MCC-2 module? Any noteworthy gotchas I should know about?
There´s a service manual by IBM. Go to IBM page and enter "maintenance manual 600" in the search field.

Sebi
swsnyder
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Sebi wrote: There´s a service manual by IBM. Go to IBM page and enter "maintenance manual 600" in the search field.
Sebi
Got it. Thanks.
beatoem
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Sharedoc wrote:Bought a 750MHz PIII-MMC2-processor from Ebay for 72 euro+delivery costs. Have to wait for the delivery 1-2 weeks.
8O i just installed a 650mmc2 on my tp 390x + it works beaut cache nall
but the wierd thing is if i leave the adsl usb modem connected it boots to 500 where as if i disconnect the usb cable let it boot then reconnect the cable in windows it runs all day at 650,anothe phenomenon is once it suspends + wake from suspend it goes back to slower speed but once i reboot again it is fine.now i'm pondering if i can somehow disable the low vcore regulator so the cpu just runs on the 1.59v regulator as like the non speedstep p111.
:( did a post mortem on that mobo that failed + it seems one of the cpu pins was severed considering the replacment board cost only $24us delivered,i was very lucky cause i purchased it as untested +was the only bidder too :D
beatoem
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swsnyder wrote:
Sebi wrote: There´s a service manual by IBM. Go to IBM page and enter "maintenance manual 600" in the search field.
Sebi
Got it. Thanks.
8) just make sure you edit the cmos before installing the p111 cpu
ad be very carefull when removing the keyboard because beneath you have the keyboard connector and the speaker connector which is very fragile and many folk ripp it out and damage the connector rather than carefully remove it with finger tip control or prying it out with a screwdiver.
have fun
beatoem
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As soon as one comes up I'm going to pick up a 750 for my PAD. Could you give detailed instructions (diagrams if you could) on how you modded your CPU. When I get hold of my own I'll write a full Mod Log with photos etc.[/quote]


no problem,when your ready send us good pics of the top +lower sections
+ill draw the locations to attend to,rest is pretty much the same as per sharedocs instructions,2.2k resistor,boot from battery first etc,i am pondering now on bypassing the lower voltage signal alltogether so full speed runs at dos/bios too as opposed to 650mghz(with 8%mod)+once it gets into windows only then it hits 810mghz mains or battery powered.
Sharedoc
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Got the 750MHz-PIII. Did the SpeedStep mod and it runs now fine the standard upper speed 750MHz.

Tried fsb overclocking, seems to run stabile 787MHz (5% fsb overclock).
However 810MHz is not stabile (8% overclock).

The heat transfer plate on top of the PIII core seems to be a bit twisted, the cooler sits on the edges on the heat transfer plate. It runs quite hot now.

When I have more time I will remover the heat transfer plate and twist it back and put some arctic silver between the core and the plate.
Sharedoc
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Sebi,

I have a hunch that the 127 error comes from MSR and MTRR register setup procedure or initial values being a bit different for PIII over PII. Therefore PIII L2 cache does not initialize correctly.

The CMOS data mod disallows L2 initialization so the 127 error does not take place.
Last edited by Sharedoc on Thu Mar 17, 2005 8:24 pm, edited 1 time in total.
Sebi
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Sharedoc,

can you point me to the code raising the 127? What checks are done before?

Unfortunately, the Intel PII/III doc says nothing special about the mtrrs, just they exist. The PII MAY report the cache via cpuid (different from PIII) - but I didn´t find cpuid being called with eax=2. Seems we have to do a little more disassembling...

Sebi
Sharedoc
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Maybe you can find the place by searching wrmsr and rdmsr instructions
or from exception handler.

Description of MSR and MTRR registers: IA32 Intel Architecture Software Developers' Manual, Vol 3: System Programming Guide.
brokencase
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You are correct. The same cache enabling code would appear in both the 600e and 600x bios's. The issue is only that the early 600e bios does not know how to identify the PIII. It can't proceed to enable the cache if it cannot id the cpu.

So what needs to be changed is how the bios id's the CPU. OR modify the code to always run the cache init.

IMHO, since a cache enabler is availible for both Linux and Windows, and that there is a workaround for the 127 error, time would be better spent in comming up with an easy way to turn on SpeedStep. This requires a hardware solution.
Sharedoc
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Brokencase,

You are right. I admire your logical deduction capability.

Let's try to find solution to SpeedStep. Now this what I have found out sofar.

Intel has a specific chip that controls SpeedStep. It propably works in a way of a special I/O device containing internal registers and it can interrupt the PIII CPU. Chip output control signal goes to VCore regulator (select Vcore = 1,35 or 1,60V) and to CPU multiplier input selection GHI#. (SpeedStep mod described in earlier messages is basically meaning: cut GHI# signal path and insert a pull-up resistor forcing GHI# = 1 always). According Intel spec "CPU latches this signal when BCLK restarts in DeepSleep state". Try figure this out, hehe.

So, with the mod, we have GHI# always 1, so we only need "BCLK restart in DeepSLeep state". It seems that CPU multiplier change does not trigger by changing GHI# alone, but it needs to be triggered somehow else (causes BCLK restart) at the right moment (CPU in DeepSleep). Propably by an interrupt generated by the SpeedStep controller?

Now what needs to be done is somehow to find out how to trigger the SpeedStep controller to generate the interrupt.

From the fact that the SpeedStep mod I detected is based on battery booting, we can deduce that power supply conditions (AC/Battery) has something to do with the Speed Step triggering conditions (DeepSleep?)

We know that all communication between 600E motherboard and SpeedStep chip go via the MMC2 connector. So there may be a signal in the connector that somehow controls/triggers the DeepSleep?

Need to go search and eyeball Intel specs.

Compare the MMC2 signals in non-SpeedStep vsSpeedStep PIII's.

I have also available both 600E and 600X motherboards to study...
Last edited by Sharedoc on Sat Mar 19, 2005 7:20 am, edited 3 times in total.
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